1. Field of the Invention
Embodiments of the invention relate to a semiconductor device and semiconductor device manufacturing method, and in particular, relate to a semiconductor device and semiconductor device manufacturing method such that a field-stop layer is provided on a substrate back surface side.
2. Related Art
An IGBT (Insulated Gate Bipolar Transistor) is a power element wherein the high speed switching characteristics and voltage drive characteristics of a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and the low on-state voltage characteristics of a bipolar transistor are configured in one chip.
IGBTs are also often used together with an FWD (free wheeling diode) or the like, and have expanded to be used in the field of industrial instruments such as general purpose and electric vehicle inverters and alternating current (AC) servos, uninterruptible power supplies (UPS), and switching power supplies, and in the field of consumer instruments such as microwave cookers, rice cookers, and stroboscopes. Furthermore, IGBTs with lower on-state voltages have been developed as elements improved to next generation types, and lower loss and higher efficiency have been achieved for applied devices.
An element using an FZ-n-type silicon (Si) substrate formed of an inexpensive FZ (Float Zone) wafer instead of a heretofore known expensive epitaxial wafer has been developed as this kind of IGBT. Furthermore, a field-stop (FS) IGBT (hereafter referred to as a trench-FS-IGBT) including a trench MOS gate (an insulated gate formed of a metal-oxide film-semiconductor) structure (hereafter referred to as a trench MOS structure) is commonly known as an IGBT. FIG. 5 is a main portion sectional view showing the configuration of a heretofore known FS-IGBT.
As shown in FIG. 5, the trench-FS-IGBT includes a plurality of trenches 11 on the front surface side of a Si substrate that forms an n− type drift layer 1. Inside the trench 11, a gate dielectric film 10 is provided along the inner wall of the trench 11, and a gate electrode 7 is provided on the inner side of the gate dielectric film 10. A p-type base layer 5 is provided in portions of the Si substrate sandwiched between the trenches 11, whereby a trench MOS structure 12 formed of the gate electrode 7, gate dielectric film 10, and p-type base layer 5 is configured on the front surface side of the Si substrate.
Furthermore, an n+ type emitter region 4 and p+ contact region 6 are selectively provided in a surface layer of the p-type base layer 5. The n+ type emitter region 4 is disposed so as to be in contact with the upper side (aperture portion side) end of a side surface of the trench 11. An emitter electrode 9 is provided forming ohmic contact to both the n+ type emitter region 4 and p-type base layer 5 (p+ contact region 6). A p+ type collector layer 3 and a collector electrode 8 are provided on the back surface side of the Si substrate. A field-stop (FS) layer 2 is provided between the p+ type collector layer 3 and n− type drift layer 1.
By using the FZ-n-type Si substrate that forms the n− type drift layer 1, it is possible to reduce the wafer cost. Also, by providing the FS layer 2, it is possible for the thickness of the Si substrate to be less than that of a non-punch through (NP) IGBT, and to be a thickness commensurate with the breakdown voltage, and thus possible to reduce the on-state voltage. Also, by the p+ type collector layer 3 being a low implantation collector that has a low dose and is shallow, it is possible to turn off at a high speed without carrying out lifetime control using electronic irradiation or the like.
A trench-FS-IGBT wherein the trench MOS structure 12, of a configuration wherein a MOS gate structure is provided on the inner walls of the trenches 11 disposed to a high density on the front surface of the semiconductor substrate, and an FS-IGBT, of a configuration wherein the FS layer 2 is provided on the back surface of the semiconductor substrate, are combined in this way is a mainstream device on the market.
As previously described, the trench-FS-IGBT shown in FIG. 5 is such that, by the FS layer 2 being provided, it is possible to reduce the on-state voltage by reducing the thickness of the Si substrate (wafer). However, a thin wafer is liable to crack during the manufacturing process, causing the efficiency rate to deteriorate, because of which a wafer that has not been thinned is used as it is when being introduced into the manufacturing process. In a subsequent process, after the trench MOS structure 12 has been formed on the front surface side of the wafer, the wafer is thinned to a thickness necessary for the breakdown voltage. A back grinding process whereby the wafer is thinned from the back surface by grinding, etching, or the like, has been proposed as a process for thinning the wafer. See, for example, JP-A-2002-299346 (also referred to herein, as “PTL 1”).
Also, a method whereby a two-stage buffer layer (FS layer), configured of a diffusion layer with a low impurity concentration formed deeply from the wafer back surface side and a diffusion layer with a high impurity concentration formed shallowly from the wafer back surface side, is formed using phosphorus (P) as the dopant for forming the FS layer or buffer layer (not shown) has been proposed as a method of improving the voltage resistance of the FS-IGBT. See, for example, JP-A-2002-261282 (also referred to herein as “PTL 2”). In PTL 2, by adopting a two-stage buffer layer, it is possible to prevent the occurrence of drain voltage and drain current oscillation, which is liable to occur when turning off. Also, it is possible to prevent an adverse effect on characteristics depending on the precision of the amount of polishing when back grinding in order to thin the wafer.
Furthermore, a method whereby the FS-layer is efficiently formed as a deep diffusion layer with a low impurity concentration using an n-type impurity such as selenium (Se) or sulfur (S), which have a higher diffusion constant than that of phosphorus, rather than phosphorus as the dopant for forming the FS layer has been proposed as a method of forming an FS-IGBT. See, for example, JP-T-2002-520885 (also referred to herein as “PTL 3”).
Also, an FS-IGBT including a structure wherein the ratio between the widths of the drift layer and depletion layer and the ratio between the impurity concentrations of the collector layer and buffer layer are each regulated has been proposed as a high breakdown voltage FS-IGBT wherein the voltage resistance in a safe operation region at a time of a short circuit current shut-off is improved. See, for example, JP-A-2010-56134 (also referred to herein as “PTL 4”).
However, in PTL 2, there is a description of a layer structure that can improve resistance to element destruction, but there is no mention of a layer structure for preventing thermal runaway destruction or a layer structure for suppressing variation in on-state voltage. Also, in PTL 4, the voltage resistance in a safe operation region at a time of a short circuit current shut-off is improved by adopting a layer configuration such that the injection efficiency of holes from the p+ type collector layer to the n-type buffer layer is high. The hole injection efficiency being high means, on the other hand, that there is concern that the leakage current will increase, which also suggests that thermal runaway destruction is liable to occur. However, no layer configuration with an advantage of preventing thermal runaway destruction is clarified in PTL 4.